1. Field of the Invention The present invention relates to a vertical field effect transistor provided with a trench-gate structure and having a current path along the sidewall of trench in a direction of thickness of substrate.
2. Description of the Related Art
Conventionally, a field effect transistor (hereinafter, referred to as MOS transistor) has been employed as one of power devices designed to withstand relatively high current densities and the application of relatively high voltages. Since the MOS transistor is the device of the type used to control its operation by means of voltage, it is advantageously able to operate without need for current input to the transistor to control its operation. Furthermore, the MOS transistor operates utilizing the lateral flow of carriers as a majority carrier that is the only one selected from an electron and a hole. On the other hand, a bipolar transistor operates utilizing the flow of the minority carriers in a vertical direction. Moreover, the bipolar transistor is forced to operate at lower speed when minority carriers accumulates within a base formed extremely thin in a vertical direction. The MOS transistor never suffers from the aforementioned undesirable accumulation of carriers. Accordingly, the MOS transistor is able to switch its state between ON and OFF at high speed. Furthermore, since the MOS transistor has a source and a drain spaced from each other by a distance longer compared with the length of base of bipolar transistor, the MOS transistor operates in a punch-through mode less potentially than the bipolar transistor. Therefore, the MOS transistor has frequently been employed as an inductive load such as a switching regulator.
The first a MOS transistor which became commercially availablewas of the type that allows operation current (drain current) to flow in a direction (lateral direction) parallel to the principal surface of a semiconductor substrate. In contrast, recently, a vertical MOS transistor has been widely used which allows drain current to flow in a direction (vertical direction) vertical to the principal surface of a semiconductor substrate. The vertical MOS transistor can advantageously increase its current capacity because the transistor can be designed to arrange a number of unit cells as a unit element in parallel with one another, constituting a MOS transistor.
For a power device designed to withstand high current densities and the application of high voltages, the on-state series resistance (hereinafter, referred to as on-resistance) and the off-state blocking voltage are important. Since the on-resistance largely affects the switching operation of the power device, the on-resistance is desirably made as small as possible. Furthermore, the off-state blocking voltage is desirably made as large as possible so as to enable the power device to withstand the application of high voltages. Therefore, for making the best of the aforementioned advantages, the vertical MOS transistor needs to reduce its on-resistance and to improve off-state blocking voltage.
FIG. 1 is a cross-sectional view of an example of a conventional vertical MOS transistor. As shown in FIG. 1, the vertical MOS transistor includes: an N.sup.+(heavily N-type doped) substrate 101; an N.sup.xe2x88x92(lightly N-type doped) layer 102, a P-type base layer 103; an N.sup.+source region 104; a trench 105; a gate insulating film 106; a gate electrode 107; an interlayer insulating film 108; a source electrode 109; a drain electrode 110; and a channel region 111. Furthermore, in the figure, L denotes spacing between trenches.
The vertical MOS transistor having the aforementioned configuration operates as follows. A specific drain voltage V.sub.DS is applied between the source electrode 109 and the drain electrode 110, and a specific gate voltage V.sub.GS is applied between the source electrode 109 and the gate electrode 107. Then, the channel region 111 of the P-type base layer 103 in the vicinity of the gate insulating film 106 is inverted to form an N-type region which is a channel that allows electric charges to flow therethrough. The inverted channel provides electrical connection between the source and drain of the transistor. At this point, the resistance between the source and drain is referred to as an on-resistance of the vertical MOS transistor.
Additionally, when the channel region between source and drain is being electrically conductive (in an on-state), the gate voltage V.sub.GS applied between the source electrode 109 and the gate electrode 107 is set to 0 volts or to a negative voltage, i.e., a reverse bias. This turns off the gate and turns the inverted channel region 111 back to a P-type region, turning an electrical path between source and drain to a nonconductive state (i.e., off-state). Thus, controlling the gate voltage V.sub.GS allows control of current flow between source and drain, and further allows the vertical MOS transistor to be employed as a power switch element.
The off-state blocking voltage BV.sub.DS of the vertical MOS transistor is defined as a drain voltage V.sub.GS that can be applied to the transistor whose gate is in an off-state. The voltage BV.sub.DS is generally determined by the dopant concentration and the thickness of the N.sup.xe2x88x92layer 102. However, in case of a vertical MOS transistor, the voltage BV.sub.DS further depends on how the surface region of the transistor is constructed. Particularly, in case of a vertical field effect transistor with a trench-gate structure, since the trench 105 penetrates the P-type base layer 103 and then protrudes into the N.sup.xe2x88x92layer 102, the blocking voltage BV.sub.DS of the transistor is determined by the distal end of the trench 105 protruding into the N.sup.xe2x88x92layer 102.
FIG. 2 is an electrical field contour plot showing simulated equipotential line distributions representing individual electric potentials of regions that range from the central portion of trench to the central portion of cell and are located around the distal end of trench in the vertical MOS transistor shown in FIG. 1. In this case, the conditions employed to determine the simulated equipotential line distributions are as follows. That is, dopant concentration of the N.sup.xe2x88x92layer 102 is 1 ohm-cm and total vertical thickness of the P-type base layer 103 and the N.sup.xe2x88x92layer 102 is 8.5 micrometers.
As can be seen from FIG. 2, when a drain voltage V.sub.DS is applied to the vertical MOS transistor, a depletion zone extends from the P-type base layer 103 to the N.sup.xe2x88x92layer 102. However, an equipotential line representing a higher potential below the boundary between the layers 103, 102 and located in the vicinity (denoted by xe2x80x9cCxe2x80x9d in FIG. 2) of the corner of the distal end of the trench 105 protruding into the N.sup.xe2x88x92layer 102 is pulled a little in a direction approaching the adjacent and lower potential line, increasing the strength of an electric field in the vicinity of the corner. Thus, the strength of an electric field in the vicinity of the corner determines the blocking voltage of transistor, voltage is lower than that of a transistor having no protrusion of the trench 105 into the N.sup.xe2x88x92layer 102.
To prevent lowering of the blocking voltage of a vertical MOS transistor having a trench-gate structure, for example, a vertical MOS transistor disclosed in U.S. Pat. No. 5,072,266 is proposed. FIG. 3 is a perspective cross-sectiona lview of the vertical MOS transistor disclosed in U.S. Pat. No. 5,072,266. The vertical MOS transistor shown in FIG. 3 has a heavily doped P-type region provided in the central portion of a P-type base layer 103 and having a depth larger than that of a trench 105. The remaining configuration of the vertical MOS transistor shown in FIG. 3 is the same as that of the conventional vertical MOS transistor.
Additionally, Japanese Patent Application Laid-open No. 8(1996)-167711 discloses a vertical MOS transistor having a P.sup.xe2x88x92layer provided between a P-type base layer and an N.sup.xe2x88x92layer, in order to prevent lowering of the blocking voltage of the transistor while maintaining a low value of the on-resistance thereof. FIG. 4 is a cross-sectional view of the vertical MOS transistor disclosed in the aforementioned publication. The vertical MOS transistor disclosed in Japanese Patent Application Laid-open No. 8(1996)-167711 includes a P.sup.xe2x88x92layer 121 formed so that the P.sup.xe2x88x92layer 121 is located between a P-type base layer 103 and an N.sup.xe2x88x92layer 102 while contacting the P-type base layer 103, and disposed facing an insulating film 106 on the trench sidewall via the N.sup.xe2x88x92layer 102. The remaining configuration of the vertical MOS transistor is the same as that of the conventional vertical MOS transistor shown in FIG. 1.
In the above-described vertical MOS transistor having the configuration shown in FIG. 3, when a drain voltage V.sub.DS is applied to the transistor, a depletion zone extends from the P-type base layer 103 to the N.sup.xe2x88x92layer 102, as is already explained in the description of the conventional vertical MOS transistor shown in FIG. 1. In this case, since the heavily doped P-type region in the central portion of a P-type base layer 103 is formed deeper than the trench 105, the degree to which an equipotential line representing a higher potential below the boundary between the layers 103, 102 and located in the vicinity of the corner of the distal end of the trench 105 is pulled in a direction approaching the adjacent and lower potential line is reduced, reducing the degree to which the blocking voltage of the transistor determined by the strength of an electric field in the vicinity of the corner of the distal end of the trench 105 is reduced. However, an equipotential line representing a higher potential located in the vicinity of the corner of the distal end of the heavily doped P-type region is pulled in a direction approaching the adjacent and lower potential line, increasing the strength of an electric field in the vicinity of the corner of the distal end of the heavily doped P-type region. Thus, the strength of an electric field in the vicinity of the corner determines the blocking voltage of transistor. Furthermore, when forming the heavily doped P-type region having a large depth, spread of a current path in the lateral direction is limited, undesirably increasing the on-resistance of the transistor.
Additionally, in case of the vertical MOS transistor, having the P.sup.xe2x88x92layer 121, of FIG. 4, when applying a drain voltage V.sub.DS to the transistor, a depletion zone also extends to the P.sup.xe2x88x92layer 121 and therefore, a decrease in the degree to which an equipotential line representing a higher potential and located in the vicinity of the corner of the distal end of the trench 105 is pulled in a direction approaching the adjacent and lower potential line is suppressed to a small extent. Accordingly, decrease in the strength of an electric field in the vicinity of the corner of the distal end of the trench 105 is suppressed to a small extent, limiting the increase in the blocking voltage BV.sub.DS of the transistor. Moreover, since avalanche breakdown occurring in an off state of the transistor easily generates carriers in the vicinity of the gate oxide film, the gate oxide film is susceptible to any damage due the carriers.
In consideration of aforementioned problems found in the conventional technique, the present invention has been conceived and therefore, is directed to a vertical MOS transistor having ability to increase its blocking voltage BV.sub.DS and constructed in a simple manner while preventing the on-resistance of the transistor from increasing and damage due to carriers generated upon avalanche breakdown of the transistor from being imposed on a gate oxide film.
A vertical MOS transistor according to the present invention includes a drain region consisting of a semiconductor layer of a first conductivity type; a base region of a second conductivity type formed on the drain region and located adjacent the drain region; a source region of a first conductivity type located within the base region and formed in a surface portion of the base region; a trench penetrating the base region and the source region to reach a part of the drain region, and extending in longitudinal and lateral directions in order to divide the base region and the source region in longitudinal and lateral directions into individual base regions and individual source regions; a gate insulating film formed on a surface of the trench; a gate electrode formed within the trench while interposing the gate insulating film between the gate electrode and the surface of the trench; a base contact region located at a approximately central portion of a region surrounded by the trench and apart from the source region, and formed deeper the base region, and further, having a higher dopant concentration than the base region. The transistor is further constructed such that when assuming a distance between a bottom and a top of the trench in a depth direction of the trench, a distance between a bottom and a top of the base region in a depth direction of the base region, and a distance between a bottom and a top of the base contact region in a depth direction of the base contact region are X.sub.a, X.sub.b and X.sub.c, respectively, the trench, the base region and the base contact region are formed so as to satisfy following mathematical relationships.
X.sub.b less than X.sub.a 
X.sub.b less than X.sub.c less than (2.times.X.sub.axe2x88x92X.sub.b) 
The vertical MOS transistor of the present invention is further constructed such that when assuming that the depth of the base contact region X.sub.c is equal to that of the trench X.sub.a, and that spacing between the trench and the base contact region is L.sub.td, the trench and the base contact region is L.sub.td are formed so as to satisfy a following mathematical relationship.
L.sub.tdxe2x89xa62.times.(X.sub.axe2x88x92X.sub.b)